1.familiar with netlist to GDSII flow, including but not limited: floorplan, place, cts, route,RC extraction, IR/EM, STA, power analyze ,PV.
2.experience on top level partition, bump assignment, RDL routing, ESD plan, feedthrough inserting, pin assignment
3.experience on top level clock tree physical implementation(H-tree,fishbone, clock mesh or other solution).
4.develop and automate top/block level backend flow
5.work with other block/top level design engineers to achieve chip signoff. Such as, IR/EM,STA,PV and so on
專業要求:不限
該職位發布已超過90天,可能已過期!